/*
 * Copyright (c) Huawei Technologies Co., Ltd. 2013-2021.
 * Description: l3 cache header file
 * Author: xiekunxun <xiekunxun@huawei.com>
 * Create: 2013-02-06
 */
#ifndef _L3_CACHE_MACRO_H
#define _L3_CACHE_MACRO_H


#define CACHE_LINE_SIZE         (64)
#define CACHE_LINE_BITSHITF     (6)

#define L3_MAXRANGE_IN_LOCK		(4096ULL)

#define L3_CTRL_REG_MASK		(0x1)
#define L3_CTRL_CACHE_DISABLE   (0)
#define L3_CTRL_CACHE_ENABLE    (1)

#define L3_MAINT_FOR_ALL        (0x0)
#define L3_MAINT_FOR_ADDR       (0x1)

#define L3_MAINT_CLEAN          (0x1)
#define L3_MAINT_INVAL          (0x2)
#define L3_MAINT_FLUSH          (0x3)

#define L3_MAINT_START          (0x1)
#define L3_MAINT_END            (0x0)

#define L3_AUCTRL_MONITOR_EN    (0x1)
#define L3_AUCTRL_EVENTBUS_EN   (0x1)

#define L3_AUCTRL_EVENT_EN_1381 (1 << 23)
#define L3_AUCTRL_ECC_EN_1381   (1 << 8)

#ifndef CONFIG_OF
#define L3_CACHE_BASE		(0xe302b000)
#define L3_CACHE_REG_LEN	(0x1000)
#endif

#define CACHE_L3_CTRL_REG           (0x0)
#define CACHE_L3_AUCTRL_REG         (0x4)
#define CACHE_L3_TIMEOUT_REG        (0x8)
#define CACHE_L3_STATUS_REG         (0xC)
#define CACHE_L3_CA_START_REG       (0x10)
#define CACHE_L3_CA_END_REG         (0x14)
#define CACHE_L3_ARAM_START_REG     (0x18)
#define CACHE_L3_ARAM_END_REG       (0x1C)

/* p650 regs diff from hi1381 */
#define CACHE_L3_SYNC_REG		(0x20)
#define P650_CACHE_L3_MAINT_CTRL_REG	(0x24)
#define CACHE_L3_MAINT_ADDR_REG		(0x28)
#define CACHE_L3_LOCKDOWN_REG		(0x2C)

/* hi1381 regs diff from p650 */
#define HI1381_CACHE_L3_MAINT_CTRL_REG	(0x20)
#define CACHE_L3_MAINT_START		(0x24)
#define CACHE_L3_MAINT_END		(0x28)

#define CACHE_L3_PREFETCH_REG       (0x30)
#define CACHE_L3_ALLOC_FREQ_REG     (0x34)

#define CACHE_L3_BANK0_EVENT_TYPE_REG   (0x180)
#define CACHE_L3_BANK1_EVENT_TYPE_REG   (0x190)
#define CACHE_L3_BANK2_EVENT_TYPE_REG   (0x1a0)
#define CACHE_L3_BANK3_EVENT_TYPE_REG   (0x1b0)
#define CACHE_L3_BANK4_EVENT_TYPE_REG   (0x1c0)
#define CACHE_L3_BANK5_EVENT_TYPE_REG   (0x1d0)
#define CACHE_L3_BANK6_EVENT_TYPE_REG   (0x1e0)
#define CACHE_L3_BANK7_EVENT_TYPE_REG   (0x1f0)
#define CACHE_L3_EVENT_TYPE_REG_OFFSET  (0x10)

#define CACHE_L3_BANK0_EVENT_CNT0_REG   (0X200)
#define CACHE_L3_BANK0_EVENT_CNT1_REG   (0X204)
#define CACHE_L3_BANK0_EVENT_CNT2_REG   (0X208)
#define CACHE_L3_BANK0_EVENT_CNT3_REG   (0X20c)

#define CACHE_L3_BANK1_EVENT_CNT0_REG   (0X210)
#define CACHE_L3_BANK1_EVENT_CNT1_REG   (0X214)
#define CACHE_L3_BANK1_EVENT_CNT2_REG   (0X218)
#define CACHE_L3_BANK1_EVENT_CNT3_REG   (0X21c)

#define CACHE_L3_BANK2_EVENT_CNT0_REG   (0X220)
#define CACHE_L3_BANK2_EVENT_CNT1_REG   (0X224)
#define CACHE_L3_BANK2_EVENT_CNT2_REG   (0X228)
#define CACHE_L3_BANK2_EVENT_CNT3_REG   (0X22c)

#define CACHE_L3_BANK3_EVENT_CNT0_REG   (0X230)
#define CACHE_L3_BANK3_EVENT_CNT1_REG   (0X234)
#define CACHE_L3_BANK3_EVENT_CNT2_REG   (0X238)
#define CACHE_L3_BANK3_EVENT_CNT3_REG   (0X23c)

#define CACHE_L3_BANK4_EVENT_CNT0_REG   (0X240)
#define CACHE_L3_BANK4_EVENT_CNT1_REG   (0X244)
#define CACHE_L3_BANK4_EVENT_CNT2_REG   (0X248)
#define CACHE_L3_BANK4_EVENT_CNT3_REG   (0X24c)

#define CACHE_L3_BANK5_EVENT_CNT0_REG   (0X250)
#define CACHE_L3_BANK5_EVENT_CNT1_REG   (0X254)
#define CACHE_L3_BANK5_EVENT_CNT2_REG   (0X258)
#define CACHE_L3_BANK5_EVENT_CNT3_REG   (0X25c)

#define CACHE_L3_BANK6_EVENT_CNT0_REG   (0X260)
#define CACHE_L3_BANK6_EVENT_CNT1_REG   (0X264)
#define CACHE_L3_BANK6_EVENT_CNT2_REG   (0X268)
#define CACHE_L3_BANK6_EVENT_CNT3_REG   (0X26c)

#define CACHE_L3_BANK7_EVENT_CNT0_REG   (0X270)
#define CACHE_L3_BANK7_EVENT_CNT1_REG   (0X274)
#define CACHE_L3_BANK7_EVENT_CNT2_REG   (0X278)
#define CACHE_L3_BANK7_EVENT_CNT3_REG   (0X27c)

/* ECC */
#define CACHE_L3_BANK0_TRAM_ECC_REG (0X300)
#define CACHE_L3_BANK0_DRAM_ECC_REG (0X304)
#define CACHE_L3_BANK0_ECC_INJECT_REG (0X308)

#define CACHE_L3_BANK1_TRAM_ECC_REG (0X310)
#define CACHE_L3_BANK1_DRAM_ECC_REG (0X314)
#define CACHE_L3_BANK1_ECC_INJECT_REG (0X318)

#define CACHE_L3_BANK2_TRAM_ECC_REG (0X320)
#define CACHE_L3_BANK2_DRAM_ECC_REG (0X324)
#define CACHE_L3_BANK2_ECC_INJECT_REG (0X328)

#define CACHE_L3_BANK3_TRAM_ECC_REG (0X330)
#define CACHE_L3_BANK3_DRAM_ECC_REG (0X334)
#define CACHE_L3_BANK3_ECC_INJECT_REG (0X338)

#define CACHE_L3_BANK4_TRAM_ECC_REG (0X340)
#define CACHE_L3_BANK4_DRAM_ECC_REG (0X344)
#define CACHE_L3_BANK4_ECC_INJECT_REG (0X348)

#define CACHE_L3_BANK5_TRAM_ECC_REG (0X350)
#define CACHE_L3_BANK5_DRAM_ECC_REG (0X354)
#define CACHE_L3_BANK5_ECC_INJECT_REG (0X358)

#define CACHE_L3_BANK6_TRAM_ECC_REG (0X360)
#define CACHE_L3_BANK6_DRAM_ECC_REG (0X364)
#define CACHE_L3_BANK6_ECC_INJECT_REG (0X368)

#define CACHE_L3_BANK7_TRAM_ECC_REG (0X370)
#define CACHE_L3_BANK7_DRAM_ECC_REG (0X374)
#define CACHE_L3_BANK7_ECC_INJECT_REG (0X378)

#define IRQ_L3_BANK0			(299)
#define CACHE_L3_BANK0_INTM_REG		(0x100)
#define CACHE_L3_BANK0_RINT_REG		(0x104)
#define CACHE_L3_BANK0_INTS_REG		(0x108)
#define CACHE_L3_BANK0_INTC_REG		(0x10c)

#define IRQ_L3_BANK1                    (300)
#define CACHE_L3_BANK1_INTM_REG         (0x110)
#define CACHE_L3_BANK1_RINT_REG         (0x114)
#define CACHE_L3_BANK1_INTS_REG         (0x118)
#define CACHE_L3_BANK1_INTC_REG         (0x11c)

#define IRQ_L3_BANK2                    (301)
#define CACHE_L3_BANK2_INTM_REG         (0x120)
#define CACHE_L3_BANK2_RINT_REG         (0x124)
#define CACHE_L3_BANK2_INTS_REG         (0x128)
#define CACHE_L3_BANK2_INTC_REG         (0x12c)

#define IRQ_L3_BANK3                    (302)
#define CACHE_L3_BANK3_INTM_REG         (0x130)
#define CACHE_L3_BANK3_RINT_REG         (0x134)
#define CACHE_L3_BANK3_INTS_REG         (0x138)
#define CACHE_L3_BANK3_INTC_REG         (0x13c)

#define IRQ_L3_BANK4                    (303)
#define CACHE_L3_BANK4_INTM_REG         (0x140)
#define CACHE_L3_BANK4_RINT_REG         (0x144)
#define CACHE_L3_BANK4_INTS_REG         (0x148)
#define CACHE_L3_BANK4_INTC_REG         (0x14c)

#define IRQ_L3_BANK5                    (304)
#define CACHE_L3_BANK5_INTM_REG         (0x150)
#define CACHE_L3_BANK5_RINT_REG         (0x154)
#define CACHE_L3_BANK5_INTS_REG         (0x158)
#define CACHE_L3_BANK5_INTC_REG         (0x15c)

#define IRQ_L3_BANK6                    (305)
#define CACHE_L3_BANK6_INTM_REG         (0x160)
#define CACHE_L3_BANK6_RINT_REG         (0x164)
#define CACHE_L3_BANK6_INTS_REG         (0x168)
#define CACHE_L3_BANK6_INTC_REG         (0x16c)

#define IRQ_L3_BANK7                    (306)
#define CACHE_L3_BANK7_INTM_REG         (0x170)
#define CACHE_L3_BANK7_RINT_REG         (0x174)
#define CACHE_L3_BANK7_INTS_REG         (0x178)
#define CACHE_L3_BANK7_INTC_REG         (0x17c)

#endif
